(1) Field of the Invention
The present invention relates to a processor with VLIW (Very Long Instruction Word) architecture, and in particular to a processor that executes instructions with comparatively short word length and high code efficiency.
(2) Description of the Prior Art
With the increase in demand for multimedia devices and the miniaturization of electronic circuits in recent years, there has been a growing need for microprocessors that can process multimedia data, such as audio data and image data, at high speed. One kind of processors that are capable of meeting this need are processors that use VLIW architecture, these being hereinafter referred to as “VLIW processors”.
VLIW processors include a number of internal operation units and so are able to simultaneously execute a number of operations in one VLIW in parallel. Such VLIW are generated by a compiler that investigates the extent to which parallel processing is possible at the source program level and performs scheduling. For embedded microprocessors used in consumer appliances, however, it is important to suppress the code size of programs, so that 256-bit VLIW, with their high incidence of no-operation instructions (hereinafter referred to as “NOP instructions”) and resulting poor code efficiency, are far from ideal.
One example of a VLIW processor that executes instructions with relative short word length is Japanese Laid-Open Patent Application H09-26878. This technique teaches a data processing apparatus that is a VLIW processor for executing 32-bit instructions that can simultaneously indicate a maximum of two operations.
FIGS. 1A and 1B show the instruction format of the stated technique, with FIG. 1A showing the instruction format for simultaneously indicating two operations and FIG. 1B showing the instruction format for indicating only one operation. This technique aims to improve code efficiency by including a 2-bit value in the format field 410 that shows the number of operations in each instruction and the execution order.
The indication of a maximum of two operations by a single 32-bit instruction, however, does not achieve a sufficient degree of parallelism. There is also the problem of decreases in code efficiency of instructions when performing an operation using a constant that exceeds a given word length. As one example, when a 32-bit constant is split into an upper 16 bits and a lower 16 bits so that it can be set into registers, two 32-bit instructions are required just to indicate an operation using this constant.